Commonly found mistakes in semiconductor/fab articles. Sadly, many chip design engineers make these mistakes too
1) TSMC/Taiwan makes >50% OR /TSMC+Samsung makes >70% of worlds IC's
Fact: That is only for foundry (contract manufacturing), not including IDMs like Intel. (1/6)
1) TSMC/Taiwan makes >50% OR /TSMC+Samsung makes >70% of worlds IC's
Fact: That is only for foundry (contract manufacturing), not including IDMs like Intel. (1/6)
2) ASML is the main tool maker for fabs. Its EUV tool is the main machine used in fabs.
Fact: ASML is one among top-5 (<20% market share). EUV litho is used probably only in 1% or so of all the litho that happens in the world & litho itself is only 1 of many many steps (2/6)
Fact: ASML is one among top-5 (<20% market share). EUV litho is used probably only in 1% or so of all the litho that happens in the world & litho itself is only 1 of many many steps (2/6)
3) ASML's tool (or similar such tools) , directly "etches" the design onto the silicon wafer
Fact: Litho tool is used to pattern on photoresist. That is then transferred to typically a hardmask and then to Silicon through other tools like RIE for the etch. In addition (3/6)
Fact: Litho tool is used to pattern on photoresist. That is then transferred to typically a hardmask and then to Silicon through other tools like RIE for the etch. In addition (3/6)
Not every layer of the design needs an etch. Some are for ion implant (doping) for example, some for deposition. Lithography is common to all layers - followed by one or more of deposition, etch, metallization, implant, chem/mech polishing etc (4/6)
4) Most chips are made using 7nm or 5nm process
Fact: By volume perhaps only <20% ICs are made in process nodes that are <20nm. Just that the revenue they bring is probably 40%+ of the whole IC revenue
This understanding has somewhat come in due to chip shortage (5/6)
Fact: By volume perhaps only <20% ICs are made in process nodes that are <20nm. Just that the revenue they bring is probably 40%+ of the whole IC revenue
This understanding has somewhat come in due to chip shortage (5/6)
Among researchers/students there is sometimes this notion that e-beam litho (SEM with writing capability) is used in industry too for litho. SEM is used in industry for inspection, but for litho, e-beam "writing" is impractical, whats used is mask based step-&-scan tools(6/6)
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